1. Field of the Invention
The present invention is related to a comparator whose power, resolution and offset are reconfigurable, and, in particular, to a comparator with calibration function.
2. Description of the Related Art
Comparators are very important building blocks in Analog to Digital Converters (ADCs) since they are the components which transfer an analog difference to the digital logic. For the ADCs without intrinsic gain and error correction between each bit quantization, such as flash or successive approximation, the comparators have a stringent requirement imposing low noise, low power and high speed of operation. In a prior art, single stage dynamic comparator shave numbers of cascading transistors from supply voltage to ground so as to limit the overdrive voltage of the input transistors. As a result, it restricts the period of the input transistors operating in saturation region and degrades the comparator's noise performance. In another prior art, a two stage dynamic comparator was presented. However, the usage of PMOS output-latch stage reduces the driving current at the load and the usage of 1st stage outputs as the clock signals of 2nd stage limits the duration for the input transistors to operate in the saturation region and leads to larger delay variation across different inputs voltage.
Besides, low noise, low offset is another critical concern in the design of ADCs. Usually, offset calibration with digital control is implemented to suppress the offset voltage by inserting unbalance capacitance at the comparator outputs or adding an extra input pair of transistors. But, these methods either degrade the speed of the comparator with extra output loads or increase its design complexity and area by adding extra bias voltage and capacitor for the calibration input transistors pair.